A conventional approach to writing to a memory responds to each data change when writing to the memory array. Pulsed wordline approaches reduce current significantly when writing and reading from memories. If the data is written to the memory array, and then changes state, the new data is written. Each time the data changes it is written to the memory array. For each data change, current is consumed to perform the write operation. Therefore, all data changes previous to the final data change consume unnecessary current. This causes the current consumption to be unpredictable during a write cycle.
Referring to FIG. 1, a circuit 10 is shown implementing a conventional pulsed wordline approach for writing to a memory. The circuit 10 generally comprises an address path block 12, a memory array block 14, a sense amplifier block 16, and output path block 18, a write driver block 20, a data transition detect block 22, an address transition detect block 24 and a control block 26. The address path block 12 and the address transition detect block 24 each receive a signal ADDRESS that is an externally generated address presented to the circuit 10. The address path block 12 presents a wordline signal WL to the memory array block 14. The memory array block 14 presents a signal TBUS to the sense amplifier block 16. The sense amplifier block 16 presents a signal SAOUT to the output path block 18. The output path block 18 presents a signal IO that may be presented to the external pins of the circuit 10. The signal IO is also presented to the write driver block 20 and the data transition detect block 22. The write driver block 20 presents data to the memory array block 14 and the sense amplifier block 16 receives data from the memory array block 14. The data transition detect block 22 presents a data transition detect signal DTD to the control block 26. The address transition detect block 24 presents an address transition detect signal ATD to the control block 26. The control block 26 also receives an external write enable signal WEB. The control block 26 also receives a signal WLDET from the memory array block 14. The control block 26 presents a signal WLEN to the address path block 12 and a signal SAEN to the sense amplifier block 16.
Referring to FIG. 2, a timing diagram illustrating the various signals of FIG. 1 is shown. The signal ADDRESS has a transition 30. The signal ATD has a positive transition 32 that responds to the transition 30 of the signal ADDRESS. The signal WEB has a transition 34 that begins the write cycle. The signal WLEN has a transition 36 that responds to the transition 34 of the signal WEB. The signal WL has a positive transition 38 that responds to the positive transition 36 of the signal WLEN. The signal WLDET has a positive transition 40 that responds to the positive transition 38 of the signal WL. The signal TBUS has a transition 42 that responds to the positive transition 40 of the signal WLDET. The signal IO has a transition 44 that responds to the negative transition 34 of the signal WEB. The period between transition 44 and 45 of the signal IO is an output tri-state time. The outputs are tri-stated so that external data can be presented on the signal IO. During the tri-state time the value of the data is uncertain. The signal DTD has a positive transition 46 that responds to the transition 44 of the signal IO. The signal IO also has a transition 45 and a transition 48. The transition 48 indicates that stable data is ready to be written to the memory array block 14. Prior to the transition 45, the signals DTD, WLEN, WL, WLDET and TBUS have uncertain states 50a-50e that represent invalid data written to the memory array block 14. Once a stable data transition 45 occurs, the signal WLDET ends the uncertain state 50d at a transition 52. The signal WLEN has a negative transition 54 that responds to the transition 52 of the signal WLDET. The signal WL has a negative transition 56 that responds to the negative transition 54 of the signal WLEN. The signal WLDET has a negative transition 58 that responds to the negative transition 56 of the signal WL. The signal TBUS has a transition 60 that responds to the negative transition 58 of the signal WLDET. The signal DTD has a positive transition 62 that responds to the transition 48 of the signal IO. The positive transition 62 of the signal DTD activates a series of transitions 36', 38', 40', 42', 54', 56', 58' and 60' which causes valid data to be written to the memory array block 14. The invalid data changes consume additional current, which is undesirable in low current applications.
The signal ADDRESS has a transition 63. The signal ATD has a transition 64 that responds to the transition 63 of the signal ADDRESS. The transition 65 of the signal WEB indicates that the circuit 10 has entered read mode. The signal ATD has a negative transition 66 that occurs after a predetermined time from the positive transition 64 of the signal ATD. The signal WLEN has a positive transition 68 that responds to the negative transition 66 of the signal ATD. The signal WL has a positive transition 70 that responds to the positive transition 68 of the signal WLEN. The signal WLDET has a positive transition 72 that responds to the positive transition 70 of the signal WL. The signal TBUS has a transition 71 that responds to the positive transition 70 of the signal WL. The signal SAEN has a positive transition 74 that responds to the positive transition 72 of the signal WLDET. The signal SAOUT has a transition 76 that responds to the positive transition of the signal SAEN. The signal IO has a transition 88 that responds to the transition 76 of the signal SAOUT, which indicates that data is read from the memory array block 14. The signal SAEN has a negative transition 78 that occurs a predetermined time after the positive transition 74 of the signal SAEN. The signal SAOUT has a transition 80 that responds to the negative transition 78 of the signal SAEN. The signal WLEN has a negative transition 82 that responds to the negative transition 78 of the signal SAEN. The signal WL has a negative transition 84 that responds to the negative transition 82 of the signal WLEN. The signal WLDET has a negative transition 86 that responds to the negative transition 84 of the signal WL. The transitions 63-88 generally represent the read operation of the circuit 10 and the transitions 30-62 generally represent the write operations of the circuit 10.